Data center and enterprise memory solution now available for customer engagement.
Cadence announced its DDR5 12.8Gbps MRDIMM Gen2 memory IP system solution on the TSMC N3 process. This solution is designed to meet the increasing memory bandwidth requirements of AI and data center applications. The DDR5 MRDIMM IP features a scalable and adaptable architecture, based on Cadence’s established DDR5 and GDDR6 product lines. The solution is already in use with AI, HPC, and data center customers.
The new Cadence DDR5 IP offers a PHY and a high-performance controller as a complete memory subsystem. The design is validated in hardware using the latest MRDIMMs (Gen2), achieving a 12.8Gbps data rate, which doubles the bandwidth of current DDR5 6400Mbps DRAM parts. The DDR5 IP memory subsystem is based on Cadence’s silicon-proven, high-performance architecture, ultra-low latency encryption and industry-leading RAS features. The DDR5 MRDIMM Gen2 IP is designed to enable advanced SoCs and chiplets with flexible floorplan design options, while the new architecture allows fine-tuning of power and performance based on individual application requirements.
Cadence’s DDR5 controller and PHY have been verified with Cadence’s Verification IP (VIP) for DDR to provide rapid IP and SoC verification closure. Cadence VIP for DDR5 includes a complete solution from IP to system-level verification with DFI VIP, DDR5 memory model and System Performance Analyzer.
For more information on the new solution, visit the Cadence DDR5 MRDIMM PHY and controller page.
